Program Verilog FPGA
Assalamualaikum Warohmatullah Wabarokatuh. Dibawah ini contoh dari program Verilog FPGA beserta pengertianya: Encoder - Using if-else Statement //----------------------------------------------------- // Design Name : encoder_using_if // File Name : encoder_using_if.v // Function : Encoder using If // Coder : Deepak Kumar Tala //----------------------------------------------------- module encoder_using_if( binary_out , // 4 bit binary output encoder_in , // 16-bit input enable // Enable for the encoder ); //-----------Output Ports--------------- output [3:0] binary_out ; //-----------Input Ports--------------- input enable ; input [15:0] encoder_in ; //------------Internal Variables-------- reg [3:0] binary_out ; //-------------Code Start----------------- always @ (enable or encoder_in) begin binary_out = 0; if (enable) begin if (encoder_in == 16'h0002) begin binary_out = 1; end if (encoder_in == 16'h0004) begin ...